Diamond-based electronics have been attractive for decades due to the intrinsic characteristics of diamond materials. With a breakdown field of at least 6 MV/cm, an electron and hole mobility greater than 2000 cm2/V/s, and a thermal conductivity greater than 20 W/cm/K, diamond transistors will continue to significantly improve the power performance of solid state radio frequency (RF) electronics, benefiting electronic systems such as, for example, phased-array radar systems, electric automobiles, and the electric power grid. Simplified thermal management and size, weight, and power (SWAP) improvements enabled by diamond technology can potentially facilitate the application of diamond electronics to high-power, solid-state, RF systems and mobile platforms such as satellites/drones.
Despite its notable properties, in terms of its development in the electronics industry, diamond has not been able to compete with other wide-band gap materials in the past due to several limitations. One limitation includes material availability, as the average size of diamond samples is typically small. However, advancements in microwave plasma chemical vapor deposition (CVD) growth technology have resulted in the availability of larger diamond samples. A second limitation includes the lack of suitable dopants for diamond, though P-type dopants such as boron are readily available. However, since boron has a relatively high activation energy of 0.36 eV, boron is particularly unsuitable for certain applications. N-type doping in diamond has been researched for decades without many significant improvements. Without overcoming these challenges, diamond electronics may never become a mainstream technology.
In consideration of these limitations and leveraging the notable properties of diamond, the technology herein presented comprises in one embodiment, a lateral, fin-based, static induction transistor (SIT) comprising diamond. SITs were introduced decades ago and they are currently used in silicon carbide (SiC) technologies. Almost all of these technologies use vertical structures with large device areas. Unfortunately, the parasitic capacitance between the gate and drain, limits the device operation in high frequency regimes. Using a lateral SIT, such as a lateral punch-through transistor, can simplify the engineering of parasitic components for high-frequency operations. However, ensuring that the device channel is properly isolated from the substrate is a big challenge when the channel comprises wide-band gap materials. Most lateral SITs have been engineered using silicon technology, where good device channel isolations are possible through a P-N junction or through silicon-on-insulator (SOI) technology. The lack of channel isolations at high voltages in lateral devices was of consideration in developing the present technology, and it is thought that by introducing a fin-based channel with an additional buffer layer to isolate the device from a semi conductive substrate, that problem may be resolved or lessened to a notable extent.